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cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 document #: 38-02023 rev. *b revised february 14, 2002 cyp15g0402dx preliminary quad hotlinkii ? serdes features ? second generation hotlink ? technology fibre-channel and gigabit-ethernet-compliant 10-bit unencoded data transport ? aggregate throughput of 12 gb/s selectable parity check/generate four independently controlled 10-bit channels selectable input clocking options user selectable framing character ? +comma, comma, or full k28.5 detect ? single or multicharacter framer for character align- ment ? low-latency option synchronous parallel input interface ? user-configurable threshold level ? compatible with lvttl, lvcmos, lvttl synchronous parallel output interface ? compatible with lvttl, lvcmos, lvttl 200-to-1500 mbaud serial signaling rate internal plls with no external pll components ? separate clock and data-recovery pll per channel ? common transmit clock multiplier pll differential pecl-compatible serial inputs differential pecl-compatible serial outputs ? source matched for 50 ? transmission lines ? no external resistors required ? adjustable amplitude for 100 ? or 150 ? balanced loads compatible with fiber-optic modules and copper cables jtag boundary scan built-in self-test (bist) for at-speed link testing per-channel link quality indicator ? analog signal detect ? digital signal detect low-power 3w typical 256-ball bga 0.25 bicmos technology functional description the cyp15g0402dx quad hotlinkii ? serdes is a point-to-point communications building block allowing the transfer of pre-encoded data over high-speed serial links (optical fiber, balanced, and unbalanced copper transmission lines) at speeds ranging from 200 to 1500 mbaud per serial link. each transmit channel accepts pre-encoded 10-bit trans- mission characters in an input register, serializes each character, and drives it out a pecl-compatible differential line driver. each receive channel accepts a serial data stream at a differential line receiver, deserializes the stream into 10-bit characters, frames these characters to the proper 10-bit character boundaries, and this data becomes register outputs with a recovered character clock. figure 1 illustrates typical connections between independent systems and a cyp15g0402dx. as a second-generation hotlink device, the cyp15g0402dx extends the hotlink family to faster data rates, while maintaining serial link compatibility with other hotlink devices. figure 1. cyp15g0402dx hotlink ii ? system connections serial links independent 10 10 10 10 10 10 10 10 system host with encoder/decoder cyp15g0402dx 10 10 10 10 10 10 10 10 serial links serial links serial links cable or optical connections channel transceiver independent channel transceiver independent channel transceiver independent channel transceiver system host with encoder/decoder
cyp15g0402dx preliminary document #: 38-02023 rev. *b page 2 of 27 the transmit section of the cyp15g0402dx quad hotlinkii serdes consists of four byte wide channels that accept a pre-encoded character on every clock cycle. transmission characters are passed from the transmit input register to a serializer. the serialized characters are output from a differ- ential transmission line driver at a bit-rate of 10 or 20 times the input reference clock. the receive section of the cyp15g0402dx quad hotlink ii serdes consists of four byte wide channels. each channel accepts a serial bit-stream from a pecl-compatible differ- ential line receiver and, using a completely integrated pll clock synchronizer, recovers the timing information necessary for data reconstruction. each recovered bit-stream is deserialized and framed into characters. recovered characters are then passed to the receiver output register, along with a recovered character clock. the lvttl parallel input interface use different clocking sources to provide flexibility in system architecture. the receive output interface may be configured to output the data with a character-rate or half character-rate clock. both true and complement recovered-clock outputs are available. each transmit and receive channel contains independent built-in self-test (bist) pattern generators and checkers. this bist hardware allows at-speed testing of the interface data path. hotlink ii devices are ideal for a variety of applications to replace parallel interfaces with high-speed, point-to-point serial links.some applications include interconnecting backplanes on switches, routers, servers and video trans- mission systems transceiver logic block diagram x10 serializer phase x10 framer deserializer tx rx x10 serializer x10 framer deserializer tx rx x10 serializer x10 framer deserializer tx rx x10 serializer x10 framer deserializer tx rx txda[9:0] rxda[9:0] txdb[9:0] rxdb[9:0] txdc[9:0] rxdc[9:0] txdd[9:0] rxdd[9:0] out a ina outb inb outc inc outd ind align buffer phase align buffer phase align buffer phase align buffer
cyp15g0402dx preliminary document #: 38-02023 rev. *b page 3 of 27 transmit path block diagram txrate character-rate clock bit-rate clock hml txclka hml hml txclkb txclkc txda[0..9] txopa input register txdb[0..9] txopb input register txdc[0..9] txopc input register txpera txperb txperc hml txclkd txdd[0..9] txopd input register 11 txperd phase-align buffer phase-align buffer phase-align buffer phase-align buffer 11 11 11 parity check bist lfsr 11 11 parity check bist lfsr 11 11 parity check bist lfsr 11 11 parity check bist lfsr 11 11 shifter 10 10 shifter shifter 10 10 shifter outa1+ outa1 ? txlba outb1+ outb1 ? txlbb outc1+ outc1 ? txlbc outd1+ outd1 ? txlbd spdsel txrst parctl parity control refclk+ refclk ? transmit pll clock multiplier txclko+ txclko ? txcksel bistle oele = internal signal bist enable latch output enable 4 8 latch boe[7..0] rbist[a..d]
cyp15g0402dx preliminary document #: 38-02023 rev. *b page 4 of 27 ina1+ ina1 ? insela txlba inb1+ inb1 ? inselb txlbb inc1+ inc1 ? inselc txlbc ind1+ ind1 ? inseld txlbd character-rate clock clock & data recovery pll shifter clock & data recovery pll shifter clock & data recovery pll shifter clock & data recovery pll shifter lpen lfid lfic lfib lfia comdetc rxdc[0..9] rxopc comdetb rxdb[0..9] rxopb comdetd rxdd[0..9] rxopd comdeta rxda[0..9] rxopa receive signal monitor receive signal monitor receive signal monitor receive signal monitor output register output register output register output register framer rxclkd+ rxclkd ? bist bist framer bist framer bist framer parity control 2 rxclkc+ rxclkc ? 2 rxclkb+ rxclkb ? 2 rxclka+ rxclka ? 2 rxrate framchar rfmode rfen sdasel jtag boundary scan controller tdo tms tclk tdi trstz receive path block diagram = internal signal rbist[a..d] rx pll enable latch rxle boe[7:0]
cyp15g0402dx preliminary document #: 38-02023 rev. *b page 5 of 27 pin configuration (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 a inc- outc - n/c n/c v cc ind- outd - gnd n/c n/c ina- outa - gnd n/c n/c v cc inb- outb - n/c n/c b inc+ outc + n/c n/c v cc ind+ outd + gndn/c n/cina+outa + gnd n/c n/c v cc inb+ outb + n/c n/c ctditmslp enc lp enb v cc par ctl sdas el gnd boe[7] boe[5] boe [3] boe [1 gnd gnd gnd v cc tx rate rx rate n/c tdo d tclk trstz lp end lp ena v cc rf mode spd sel gnd boe[6] boe[4] boe [2] boe [0] gnd gnd gnd v cc n/c rxle n/c n/c ev cc v cc v cc v cc v cc v cc v cc v cc ftx perc tx opc txdc [0] rxck sel bistl e rxdb [0] rxop b rxdb [1] gtxdc [7] txck sel txdc [4] txdc [1] gnd oele fram char ] rxdb [3] h gnd gnd gnd gnd gnd gnd gnd gnd jtxdc [9] txdc [5] txdc [2} txdc [3] comd etb rxdb [2] rxdb [7] rxdb [4] krxdc [4] rx clkc - txdc [8] lfic rxdb [5] rx db[6] rxdb [9] rx clk b+ lrxdc [5] rx clkc + txclk c txdc [6] rxdb [8] lfib rxcl k b- txdb [6] mrxdc [6] rxdc [7] rxdc [9] rxdc [8] txdb [9] txdb [8] tx db[7] tx clkb n gnd gnd gnd gnd gnd gnd gnd gnd prxdc [3] rxdc [2] rxdc [1] rxdc [0] txdb [5] txdb [4] tx db[3] tx db[2] rcom detc rx opc tx perd tx opd txdb [1] txdb [0] tx opb tx perb tv cc v cc v cc v cc v cc v cc v cc v cc utxdd [0] txdd [1] txdd [2] txdd [9] v cc rxdd [4] rxdd [3] gnd rx opd rf enc refc lk - txda [1] gnd txda [4] txda [8] v cc rxda [4] rx opa com deta rx da[0] vtxdd [3] txdd [4] txdd [8] rx dd[8] v cc rxdd [5] rxdd [1] gnd com detd rf end refc lk + rfen b gnd txda [3] txda [7] v cc rxda [9] rx da[5] rx da[2] rx da[1] wtxdd [5] txdd [7] lfid rx clk d ? v cc rxdd [6] rxdd [0] gnd tx clk o ? tx rst tx opa rfen a gnd txda [2] txda [6] v cc lfia rx clk a ? rx da[6] rx da[3] ytx dd[6] tx clkd rxdd [9] rx clk d+ v cc rxdd [7] rxdd [2] gnd tx clk o+ n/c tx clka tx pera gnd txda [0] txda [5] v cc txda [9] rx clk a+ rx da[8] rx da[7]
cyp15g0402dx preliminary document #: 38-02023 rev. *b page 6 of 27 pin configuration (bottom view) 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 an/cn/coutb - inb- v cc n/c n/c gnd outa - ina- n/c n/c gnd outd - ind- v cc n/c n/c outc - inc- b n/c n/c outb+ inb+ v cc n/c n/c gnd outa + ina+ n/c n/c gnd outd+ ind+ v cc n/c n/c outc + inc+ ctdon/crx rate tx rate v cc gnd gnd gnd boe [1 boe [3] boe[5] boe[7] gnd sdasel par ctl v cc lp enb lp enc tms tdi d n/c n/c rxle n/c v cc gnd gnd gnd boe [0] boe [2] boe[4] boe[6] gnd spd sel rf mode v cc lp ena lp end trstz tclk e v cc v cc v cc v cc v cc v cc v cc v cc frxdb [1] rxopb rxdb [0] bistle rxcks el txdc [0] tx opc tx perc grxdb [3] fram char ] oele gnd txdc [1] txdc [4] txck sel txdc [7] h gnd gnd gnd gnd gnd gnd gnd gnd jrxdb [4] rxdb [7] rxdb [2] comde tb txdc [3] txdc [2} txdc [5] txdc [9] krx clk b+ rxdb [9] rx db[6] rxdb [5] lfic txdc [8] rx clkc - rxdc [4] ltxdb [6] rxclk b- lfib rxdb [8] txdc [6] txclk c rx clkc+ rxdc [5] mtx clkb tx db[7] txdb [8] txdb [9] rxdc [8] rxdc [9] rxdc [7] rxdc [6] n gnd gnd gnd gnd gnd gnd gnd gnd ptx db[2] tx db[3] txdb [4] txdb [5] rxdc [0] rxdc [1] rxdc [2] rxdc [3] rtx perb tx opb txdb [0] txdb [1] tx opd tx perd rx opc com detc t v cc v cc v cc v cc v cc v cc v cc v cc urx da[0] com deta rx opa rxda [4] v cc txda [8] txda [4] gnd txda [1] refclk - rf enc rx opd gnd rxdd [3] rxdd [4] v cc txdd [9] txdd [2] txdd [1] txdd [0] vrx da[1] rx da[2] rx da[5] rxda [9] v cc txda [7] txda [3] gnd rfen b refclk + rf end com detd gnd rxdd [1] rxdd [5] v cc rx dd[8] txdd [8] txdd [4] txdd [3] wrx da[3] rx da[6] rx clk a ? lfia v cc txda [6] txda [2] gnd rfen a tx opa tx rst tx clk o ? gnd rxdd [0] rxdd [6] v cc rx clk d ? lfid txdd [7] txdd [5] yrx da[7] rx da[8] rx clk a+ txda [9] v cc txda [5] txda [0] gnd tx pera tx clka n/c tx clk o+ gnd rxdd [2] rxdd [7] v cc rx clk d+ rxdd [9] tx clkd tx dd[6]
cyp15g0402dx preliminary document #: 38-02023 rev. *b page 7 of 27 pin descriptions quad hotlink ii serdes name i/o characteristics signal description transmit path data signals txpera txperb txperc txperd lvttl output, changes following txclko transmit path parity error . active high parity checking must be enabled and a parity error will be detected. this output is high for one txclko clock period to indicate detection of a parity error in the character presented to the shifter. when parity error is detected, the character in error is replaced with a +c0.7 character to force a corre- sponding bad character detection at the remote end of the link. this replacement takes place only when parity checking is enabled (parctl low). when bist is enabled for a transmit channel, bist progress is presented on the associated txperx output. once every 511 character times, txperx pulses high for one txclko period to indicate a complete pass through the bist sequence. when the transmit phase align buffers are enabled (txcksel low), if an underflow or overflow condition is detected, txperx for that channel is asserted and remains asserted until reset by txrst . txda[9:0] txdb[9:0] txdc[9:0] txdd[9:0] lvttl input, synchronous, sampled by the respective txclkx or txclko transmit data inputs . these inputs are captured on the rising edge of the transmit interface clock and passed to the transmit shifter. txdx[9:0] specify the specific trans- mission character to be sent. txopa txopb txopc txopd lvttl input, synchronous, sampled by the respective txclkx or txclko transmit path odd parity . when parity checking is enabled (parctl low), the odd parity captured at these inputs is xored with the bits on the associated txdx bus to verify the integrity of the captured character. transmit path clock and control txclko lvttl output transmit clock output . this true and complement clock is synthesized by the transmit pll and is synchronous to the internal transmit character clock. it operates at either the same frequency as refclk, or at twice the frequency of refclk. txclko is always equal to the vco bit-clock frequency 10. the txclko+ output rising edges and txclko ? falling edges are phase aligned to the rising edges of the refclk input. txrst lvttl input, asynchronous transmit clock phase reset, active low . when low, the transmit phase align buffers are allowed to adjust their data transfer timing to allow clean transfer of data from the input register to the transmit shifter. when txrst is high, the internal phase relationship between the selected txclkx and the internal character-rate clock is fixed. during this reset alignment period, one or more characters may be added to or lost from all the associated transmit paths as the transmit elasticity buffers are adjusted. txcksel 3-level select [1] static control input transmit clock select . selects the clock source used to write data into the transmit input register. when low, all four input registers are clocked by the internal txclko derivative of refclk. when txcksel is mid, txclkx is used as the input register clock for the associated txdx[9:0] and txopx. when high, txclka is used to clock data into the input register for all channels. txrate lvttl input, asynchronous, internal pull-up transmit pll clock rate select . when txrate = high, the transmit pll multiplies refclk by 20 to generate the serial bit-rate clock. when txrate = low, the transmit pll multiples refclk by 10 to generate the serial bit-rate clock. see table 3 for a list of operating serial rates. when refclk is selected for clocking of the receive parallel interfaces, the txrate input also determines if the clock on the rxclka and rxclkc outputs is a full or half-rate clock. when txrate = high, these clocks are half-rate clocks. when txrate = low, these output clocks are full-rate clocks and follow the frequency and duty cycle of the refclk input. txclka txclkb txclkc txclkd lvttl clock input asynchronous, internal pull-up transmit path input clocks . these inputs are only used when txcksel low. these clocks are frequency coherent to txclko , but may be offset in phase. operating phase is adjusted when txrst is low; and phase locked when txrst is high.
cyp15g0402dx preliminary document #: 38-02023 rev. *b page 8 of 27 receive path data signals rxda[9:0] rxdb[9:0] rxdc[9:0] rxdd[9:0] lvttl output, synchronous receive data output . these outputs change following the rising edge of the associated rxclkx clock. comdeta comdetb comdetc comdetd lvttl output, synchronous frame character detected . the character in the output register matches that of the selected framing character. rxopa rxopb rxopc rxopd three-state, lvttl output receive path odd parity . when parctl isn ? t low parity generation is enabled, the parity output at these pins is valid for the data on the associated rxdx bus bits. when parctl=low parity generation is disabled, these output drivers are high-z. rxrate lvttl input static control input receive clock rate select . when low, the rxclkx recovered clock outputs are complementary clocks operating at the recovered character rate. data for the associated receive channels should be latched on the rising edge of rxclkx+ or falling edge of rxclkx ? . when high, the rxclkx recovered clock outputs are complementary clocks operating at half the character rate. data for the associated receive channels should be latched alternately on the rising edge of rxclkx+ and rxclkx ? . when operating with refclk clocking of the received parallel data outputs both rxcksel and rxrate must be low. refclk differential lvpecl or single-ended lvcmos input clock reference clock . this clock input is used as the timing reference for the transmit and receive plls. this input clock may also be selected to clock the transmit and receive parallel interfaces. for an lvcmos or lvttl input clock connect clock source to refclk to the input pin and float the other refclk ? . for an lvpecl input level input clock has to be a differential clock, using both inputs. for an lvpecl differential clock, both inputs must have a phase difference of 180 degrees. when txcksel is low, a character-rate derivative of refclk is used as the clock for the parallel transmit data input interface. spdsel 3-level select [1] , static control input serial rate select . this input specifies the operating bit-rate range of both transmit and receive plls. low = 200 ? 400 mbaud, mid = 400 ? 800 mbaud, high = 800 ? 1500 mbaud. analog i/o and control outa outb outc outd cml differential output differential serial data outputs . these cml outputs are capable of driving terminated transmission lines or standard fiber-optic transmitter modules. ina inb inc ind lvpecl differential input differential serial data inputs . these inputs accept the serial data stream for deseri- alization and decoding. the inx serial stream is fed to the receiver to extract the data and clock content when lpenx is low. sdasel 3-level select [1] , static configuration input signal detect amplitude level select . allows selection of one of three predefined amplitude trip points for a valid signal indication, as listed in table 4 . lpena lpenb lpenc lpend lvttl input, asynchronous, internal pull-down loop-back-enable . when high, the transmit serial data from the associated channel is internally routed to its respective receiver clock and data recovery (cdr) circuit. the serial output for the channel where lpenx is active is forced to differential logic-1, and serial data inputs for that channel are ignored. pin descriptions quad hotlink ii serdes name i/o characteristics signal description
cyp15g0402dx preliminary document #: 38-02023 rev. *b page 9 of 27 oele lvttl input, asynchronous, internal pull-up serial driver output enable latch enable . when oele = high, the signals on the boe[7:0] inputs directly control the outx differential drivers. when the boe[x] input is high, the associated outx differential driver is enabled. when the boe[x] input is low, the associated outx differential driver is powered down. when oele returns low, the last values boe[7:0] are captured. the specific mapping of boe[7:0] signals to transmit output enables is listed in table 2 . if the device is reset, the latch is reset to enable all outputs. bistle lvttl input, asynchronous, internal pull-up transmit and receive bist latch enable . when bistle = high, the signals on the boe[7:0] inputs directly control the transmit and receive bist enables. when boe[x] input is low, the associated transmit or receive channel is configured to generate or compare the bist sequence. when the boe[x] input is high, the associated transmit or receive channel is configured for normal data mode. when bistle returns low, value present on boe[7:0] is captured. the specific mapping of boe[7:0] signals to transmit and receive bist enables is listed in table 2 . if the device is reset, this enable latch is reset to disable bist on all transmit and receive channels. rxle lvttl input, asynchronous, internal pull-up receive channel power-control latch enable . when rxle = high, the signals on the boe[7:0] directly control the power enables for the receive plls and analog logic. when the boe[7:0] input is high, the all receive channels pll ? s and analog logic are active. when the boe[7:0] input is low, all the receive channels are in a power down mode. when rxle returns low, boe[7:0] values are captured. the specific mapping of boe[7:0] signals to the associated receive channel enables is listed in table 2 . if the device is reset, the latch is reset to enable all receive channels. boe[7:0] lvttl input, asynchronous, internal pull-up bist, serial output, and receive channel enables . these inputs are passed through the output enable latch when oele is high, and captured in this latch when oele returns low. these inputs are passed through the bist enable latch when bistle is high, and captured in this latch when bistle returns low. these inputs are passed through the receive channel enable latch when rxle is high, and captured in this latch when rxle returns low. lfia lfib lfic lfid lvttl output, changes following rxclkx link fault indication output . active low. lfi* is the logical or of three internal conditions on the associated channel: 1. received serial data frequency outside expected range; 2. analog amplitude below expected levels; and 3. transition density lower than expected. jtag interface tms lvcmos input, internal pull-up test mode select. enables jtag test mode tclk lvcmos input, internal pull-down jtag test clock tdo three-state lvcmos output test data out . jtag data output buffer which is high-z while jtag test mode is not selected. tdi lvcmos input, internal pull-up test data in . jtag data input port. trstz lvcmos input, internal pull-up test reset . jtag and full chip reset. active low. initializes the jtag controller and all other state machines. power v cc +3.3v power gnd signal and power ground for all internal circuits pin descriptions quad hotlink ii serdes name i/o characteristics signal description
cyp15g0402dx preliminary document #: 38-02023 rev. *b page 10 of 27 name i/o characteristics signal description framchar 3-level select [1] static control input framing character select. used to control the type of character used for framing the received data streams. when low, the framer looks for an 8-bit positive comma character in the data stream. when mid, the framer looks for both positive and negative disparity versions of the 8-bit comma character. when high, the framer looks for both positive and negative disparity versions of the k28.5 character. rfmode 3-level select [1] static control input reframe mode select. used to control the type of character framing system. this signal operates in conjunction with the presently enabled channel bonding mode, and the type of framing character selected. when low, the low-latency framer is selected. this will frame on the first occurrence of the selected framing character in the received data stream. this framing mode stretches the recovered clock for multiple cycles to align that clock with the recovered data. when mid, the cypress-mode multi-byte parallel framer is selected. this requires a pair of the selected framing character, on identical 10-bit boundaries, within a span of 50 bits, before the character boundaries are adjusted. the recovered character clock remains in the same phasing regardless of character offset. when high, the alternate mode multi-byte parallel framer is selected. this requires detection of the selected framing character of the allowed disparities in the received data stream, on identical 10-bit boundaries, on four directly adjacent characters. the recovered character clock remains in the same phasing regardless of character offset. receive path clock and clock control rxclka rxclkb rxclkc rxclkd three-state, lvttl output clock static control input receive character clock . these true and complement clocks are the receive interface clocks which are used to control timing of data output transfers. these clocks are output continuously at either character rate of 1/20th or 1/10th the serial bit-rate of the input data. rfena rfenb rfenc rfend lvttl input, asynchronous, internal pull-down reframe enable . active high. when high the framer for the associated channel is enabled to frame as per the framing mode and selected framing character. rxcksel 3-level select [1] static control input receive clock mode . selects the receive clock-source used to transfer data to the output registers. when low, all four output registers are clocked by refclk. rxclkb and rxclkd outputs are disabled (high-z), and rxclka and rxclkc present buffered and delayed forms of refclk. this clocking mode is required for channel bonding across multiple devices. when mid, each rxclkx output follows the recovered clock for the respective channel, as selected by rxrate. when high, and channel bonding is enabled in dual-channel mode (rx modes 3 and 5), rxclka outputs the recovered clock from either receive channel a or receive channel b as selected by rxclkb+, and rxclkc outputs the recovered clock from either receive channel c or receive channel d as selected by rxclkd+. these output clocks may operate at the character-rate or half the character-rate as selected by rxrate. when high and channel bonding is enabled in quad channel mode (rx modes 6 and 8), or if the receive channels are operated in independent mode (rx modes 0 and 2), rxclka and rxclkc output the recovered clock from receive channel a, b, c, or d, as selected by rxclkb+ and rxclkd+. this output clock may operate at the character-rate or half the character-rate as selected by rxrate. device control signals parctl 3-level select [1] , static control input parity check/generate control . used to control the different parity checks. when low, parity checking and generation are disabled, and the rxopx output drivers are disabled. when mid, the txdx[9:0] inputs are checked, along with txopx, for valid odd parity, and valid odd parity is generated for the rxdx[9:0] outputs and presented on rxopx. when high, the txdx[9:0] inputs are checked, along with txopx, for valid odd parity. valid odd parity is generated for the rxdx[9:0] and comdetx outputs and presented on rxopx. note: 1. 3-level select inputs are used for static configuration. they are ternary (not binary) inputs that make use of non-standard l ogic levels of low, mid, and high. the low level is usually implemented by direct connection to v ss (ground). the high level is usually implemented by direct connection to v cc (power). when not connected or allowed to float, a 3-level select input will self-bias to the mid level.
cyp15g0402dx preliminary document #: 38-02023 rev. *b page 11 of 27 cyp15g0402dx hotlink ii serdes operation the cyp15g0402dx is designed to support transfer of large quantities of data, using high-speed serial links. this device contains four byte wide channels. cyp15g0402dx transmit data path data path the transmit path of the cyp15g0402dx supports four character-wide data paths. these four data paths are inter- nally unencoded and require input data that is encoded for reliable transport. input register the bits in the input register for each channel have fixed bit assignments, as listed in table 1 . each input register captures 10 bits on each input clock cycle. when parity checking is enabled, the txopx parity input is also captured in the associated input register. input register clocking the transmit input registers can be configured to accept data relative to different clock sources. the selection of the clock source is controlled by txcksel. when txcksel is low, the transmit input registers capture data synchronous to the txclko a derivative of refclk. when txcksel is mid, the rising edge of txclk is used to capture the data at the associated txdx[9:0] and txopx inputs. when txcksel is high, the rising edge of txclka is used to capture the data at the associated txdx[9:0] and txopx inputs on all four channels. phase-align buffer data from the input registers is normally routed to the associated phase-align buffer. if the transmit input registers are configured to capture data synchronous to refclk (txcksel = low), the phase-align buffers are bypassed and data is passed directly to the parity check and serializer blocks. when the input registers are clocked with refclk and txcksel low, the phase-align buffers are enabled. these buffers will absorb clock phase differences between the presently selected input clock and the internal character clock. txrst when low will initialize the phase-align buffers. when txrst is returned high, the present input clock phase relative to refclk is set. once set, the input clocks are allowed to skew in time up to half a character period in either direction relative to refclk. this time-shift allows the delay paths of the character clocks to change due to operating voltage and temperature, while not affecting operation. parity support in addition to the ten data and control bits that are captured at each channel, a txopx input is also available on each channel. this allows the cyp15g0402dx to support odd parity checking for each channel. when parctl is low, parity checking is disabled. when parctl is mid or high, parity is checked on the txdx[9:0] and txopx bits. if parity checking is enabled (parctl low) and a parity error is detected, the 10-bit character in error is replaced with the 1001111000 pattern an invalid character. transmit bist the transmitter interfaces contains an internal bist pattern generators that can be used to validate both device and link operation. this generator is enabled by the associated boe[x] signals listed in table 2 and when bistle latch enable input is high. when enabled, a register in the associated transmit channel becomes a pattern generator. this 511-character sequence that includes all data and special character codes, including the explicit violation symbols. this provides a predictable yet pseudo-random sequence that can be matched to an identical receiver. when the bistle signal is high, any boe[x] input that is low enables the bist generator in that associated transmit channel or the bist checker in the associated receive channel. when bistle returns low, the values of all boe[x] signals are captured in the bist enable latch. bist is disabled following a device reset by trstz . all data and data-control information present at the associated txdx[7:0] and txctx[1:0] inputs are ignored when bist is active on that channel. if the receive channels are configured for common clock operation (rxcksel mid) each pass is preceded by a 16-character word sync sequence to allow elasticity buffer alignment and reset of clock phase. table 1. input register bit mapping signal name bus weight 10b name txdx[0] (lsb) 2 0 a [2] txdx[1] 2 1 b txdx[2] 2 2 c txdx[3] 2 3 d txdx[4] 2 4 e txdx[5] 2 5 i txdx[6] 2 6 f txdx[7] 2 7 g txdx[8] 2 8 h txdx[9] (msb) 2 9 j txopx [3] notes: 2. lsb is shifted out first. 3. the txopx inputs are also captured in the associated input register, but their interpretation is under the separate control o f parctl.
cyp15g0402dx preliminary document #: 38-02023 rev. *b page 12 of 27 serial output drivers the serial interface output drivers make use of differential current mode logic to provide a source-matched driver for the transmission lines. these drivers accept data from the transmit shifters. these outputs have signal swings equiv- alent to that of standard pecl drivers, and are capable of driving ac-coupled optical modules or transmission lines. when configured for internal local loopback test, lpen = high, the output drivers for all enabled ports are configured to drive a static differential logic-1. each output can be enabled or disabled separately through the boe[7:0] inputs, as controlled by the oele latch-enable signal. when oele is high, the signals present on the boe[7:0] inputs are passed through the serial output enable latch to control the serial output drivers. the boe[7:0] input associated with a specific outx driver is listed in table 2 . when oele is high and boe[x] is high, the associated serial driver is enabled. when oele is high and boe[x] is low, the associated driver is disabled and in a power down mode. if both outputs for a channel are disabled, the associated internal logic for that channel is also configured for low power operation. when oele returns low, the values present on the boe[7:0] inputs are latched in the output enable latch, and remain there until oele returns high to opened the latch again. note . when a disabled transmit channel is re-enabled, the data on the serial outputs may not meet all timing specifications for up to 10 ms. transmit pll clock multiplier the transmit pll clock multiplier accepts a character-rate or half-character-rate external clock at the refclk input, and multiplies that clock by 10 or 20 to generate a bit-rate clock for use by the transmit shifter. the clock multiplier pll can accept a refclk input between 10 mhz and 150 mhz, however, this clock range of the pll is controlled by the txrate and spdsel input signals of the cyp15g0402dx. spdsel is a 3-level select [1] (ternary) input that selects one of three operating ranges for the serial data outputs and inputs. the operating serial signalling rate and allowable range of refclk frequencies is listed in table 3 . the refclk input is a differential input with each input inter- nally biased to 1.5v. if the refclk+ input is connected to a ttl, lvttl, or lvcmos clock source, the input signal is recognized when the clock signal passes through the internal biased point. when both the refclk+ and refclk ? inputs are connected, the clock source must be a differential clock. this can be either a lvpecl clock, or a differential lvttl or lvcmos clock. table 2. output enable, bist, and receive channel enable signal map boe input output controlled (oele) bist channel enable (bistle) receive pll channel enable (rxle) boe[7] x transmit d x boe[6] outd receive d receive d boe[5] x transmit c x boe[4] outc receive c receive c boe[3] x transmit b x boe[2] outb receive b receive b boe[1] x transmit a x boe[0] outa receive a receive a table 3. operating speed settings spdsel txrate refclk frequency (mhz) signaling rate (mbaud) low 1 20 200 ? 400 020 ? 40 mid (open) 1 20 ? 40 400 ? 800 040 ? 80 high 1 40 ? 75 800 ? 1500 080 ? 150
cyp15g0402dx preliminary document #: 38-02023 rev. *b page 13 of 27 cyp15g0402dx receive data path serial line receivers a differential line receiver, inx , is on each channel for accepting a serial bit stream. the serial line receiver inputs are differential needing only 100mv pp ac differential input. the input can be dc- or ac-coupled to +3.3v powered fiber-optic interface modules with a ecl/pecl output level. the input could be ac-coupled to +5v powered optical modules. the common-mode tolerance of these line receivers accommo- dates a wide range of input signals. the local loopback input (lpenx) for each channel allows the serial transmit data for the associated channel to be routed internally back to the clock and data recovery circuit associated with that channel. when a channel is configured for local loopback, the associated transmit serial driver outputs are forced to output a differential logic-1. this prevents local diagnostic patterns from being broadcast to attached remote receivers or optical drivers. receive channel enabled the cyp15g0402dx contains four receive channels that can be independently enabled and disabled. each channel can be enabled or disabled separately through the boe[7:0] inputs, as controlled by the rxle latch-enable signal. when rxle is high, the signals present on the boe[7:0] inputs are passed through the receive channel enable latch to control the plls and logic of the associated receive channel. the boe[7:0] input associated with a specific receive channel is listed in table 2 . when rxle and boe[x] are high, the associated receive channel is enabled to receive a serial stream from the selected line receiver. when rxle is high and boe[x] is low, the associated receive channel is disabled and powered down. signal detect each line receiver is simultaneously monitored for: analog amplitude transition density received data stream outside normal frequency range (200 ppm). all of these conditions must be valid for the signal detect block to indicate a valid signal is present. this status is presented on the lfix (link fault indicator) output associated with each receive channel. these lfix outputs change synchronous to the receive interface recovered clock. while the majority of these signal monitors are based on fixed constants, the analog amplitude level detection is adjustable to allow operation with attenuated signals. this adjustment is made through the sdasel signal, a 3-level select [1] input, which sets the trip point for the detection of a valid signal at one of three levels, as listed in table 4 . sdasel input controls the analog monitors for all receive channels. clock/data recovery the extraction of a bit-rate clock and recovery of bits from each received serial stream is performed by a separate clock/data recovery (cdr) block within each channel. the clock extraction function is performed by embedded phase-locked loops that track the frequency and phase of transitions of the incoming bit streams. each cdr accepts a character-rate or half-character-rate reference clock on the refclk input. this refclk input is used to ensure that the vco is operating at the correct frequency. the use of the refclk improves pll acquisition time, and limits the unlocked frequency excursions of the vco when there is no input data. regardless of the type of input signal, the cdr will attempt to recover a data stream. if the frequency of the recovered data stream is outside the limits set by the integrated range controls, the pll reference will switch to refclk. when the frequency of the selected data stream returns to a valid frequency, the cdr pll is allowed to track the received data stream. the frequency of refclk is required to be within 200 ppm of the frequency of the clock that drives the refclk signal of the remote transmitter to ensure a lock to the incoming data stream. deserializer/framer each cdr circuit extracts bits from the associated serial data stream and clocks these bits into the shifter/framer at the bit-clock rate. when enabled, the framer examines the data stream looking for one or more comma or k28.5 characters at all possible bit positions. the location of this character in the data stream is used to determine the frame of the characters that follow. framing character the cyp15g0402dx allows selection of one of three combi- nations of framing characters to support requirements of different interfaces. the selection of the framing character is made through the framchar input. framchar is a 3-level select [1] input that allows selection of one of three different characters or character combinations. these combinations are listed in table 5 . framer the framer on each channel operates in one of three different modes, as selected by the rfmode input. when rfmode is low, the low-latency framer is selected. this framer operates by stretching the recovered character clock until it aligns with the character boundaries. in this mode the framer aligns on the first detection of the selected framing character. when rfmode is mid the cypress-mode multi-character framer is selected. the detection of multiple framing table 4. analog amplitude detect valid signal levels sdasel typical signal with peak amplitudes above low 140 mv p-p differential mid (open) 280 mv p-p differential high 420 mv p-p differential table 5. framing character selector framchar bits detected in framer character name bits detected low +comma 00111110xx mid (open) +comma ? comma 00111110xx or 11000001xx high +k28.5 ? k28.5 0011111010 or 1100000101
cyp15g0402dx preliminary document #: 38-02023 rev. *b page 14 of 27 characters makes the associated link much more robust to incorrect framing. in this mode the framer does not adjust the character clock boundary, but instead aligns the character to the already recovered character clock. this ensures that the recovered clock will not contain any significant phase changes or hops during normal operation. this allows the recovered clock to be distributed to other external circuits. in this framing mode the character boundaries are only adjusted if the selected framing character is detected at least twice within a span of 50 bits, with both instances on identical 10-bit character boundaries. when rfmode is high, the alternate-mode multi-character framer is enabled. like cypress-mode multi-character framing, multiple framing characters must be detected to adjust the character boundaries. in this mode, the data stream must contain a minimum of four of the selected framing characters, received as consecutive characters, before character framing is adjusted. in systems that use 8b/10b coding running disparity rules prohibit the presence of multiple +comma characters as consecutive characters, except for the k28.7 comma character. because of this, the combination of framchar low and rfmode high is not recommended. while framing can still take place while following all 8b/10b coding rules, this configuration prevents framing to the normal k28.5 character. framing is enabled for a channel when the associated rfenx input is high. when rfenx is low, the framer for the associated channel is disabled. when a framer is disabled, no changes are made to the recovered character boundaries on that channel, regardless of the presence of framing characters in the data stream. bist lfsr the output register of each framer is normally used to pass received characters to the associated output register. when configured for bist mode, this register becomes a signature pattern generator. when in the bist mode, a 511-character sequence is generated that includes all data and special character codes, including the explicit violation symbols.this provides a predictable but pseudo-random sequence that can be matched to an identical lfsr in the attached trans- mitter(s). when synchronized with the received data stream, the associated receiver checks each character received with each character generated by the lfsr and indicates compare errors and bist status at the rxdx[2:0] bits of the output register. these generators are enabled by the associated boe[x] signals listed in table 2 (when the bistle latch enable input is high).when the bistle signal is high, any boe[x] input that is low enables the bist generator/checker in the associated receive channel. when bistle returns low, the values of all boe[x] signals are captured in the bist enable latch.these values remain in the bist enable latch until bistle is returned high to resample the input again. all captured signals in the bist enable latch are set high and bist is disabled following a device reset by trstz . the lfsr is initialized by the bist hardware once the external enable (rxbistenx ) is recognized. the enable resets the bist lfsr to the bist-loop start-code of d0.0. d0.0 is sent only at the beginning of the bist loop. the status of the bist progress and any character mismatches is appears as an output on the rxdx[2:0] outputs. code rule violations or running disparity errors the bist loop will not cause an error indication. rxdx[2:0] indicates 01x for one rxclk cycle per bist loop to indicate loop completion. this can be used to check test pattern progress. the specific patterns checked by each receiver are described in detail in the cypress application note ? hotlink built-in self-test. ? the sequence compared by the cyp15g0402dx is identical to that in the cy7b933 and cy7c924, allowing interoperable systems to be built when used at compatible serial signalling rates. if a large number of errors are detected, the receive bist state machine aborts the compare operations and resets the lfsr to look for the start of the bist sequence again. power control the chip can be powered down one channel at a time. the channel to be selected is controlled by boe[7:0] latch. both the transmit and the receive channels are controlled by a receive channel power latch and the transmit channel is controlled by an output enable control system. powering down table 6. bist status bits status priority description comdetx rxdx[0] rxdx[1] bist mode (rxbisten is low) 0 007 bist data compare. data character compared correctly. 0 017 bist command compare. command character compared correctly. 0 102 bist last good. last character of bist sequence detected and valid. 0 115reserved 1 004 bist last bad. last character of bist sequence was detected invalid. 1 011 bist start. rxbisten recognized on this channel, but character compares have not yet commenced. also presented when the receive pll is tracking refclk instead of the selected data stream. 1 106 bist error. while comparing characters, a mismatch was found in one or more of the decoded character bits. 1 113 bist wait. the receiver is comparing characters. but has not yet found the start of bist character to enable the lfsr.
cyp15g0402dx preliminary document #: 38-02023 rev. *b page 15 of 27 channels will save considerable power and will reduce system heat generation. controlling system power dissipation will improve the system reliability. receive channel power-control latch enable. active high. when rxle is high, the signals on the boe[7:0] inputs directly control the power enables for the receive plls and analog circuits. when the boe[7:0] input is high, the associated receive channel [a.d] plls and analog logic are active. when the boe[7:0] input is low, the associated receive channel [a.d] pll ? s and analog circuits are in a power down mode. when rxle returns low, the last values present on boe[7:0] are captured. the channels controlled by boe[7:0] signals are listed in table 2 . when rxle is high and boe[x] is high, the associated receive channel is enabled to receive a serial stream from the selected line receiver. when rxle is high and boe[x] is low, the associated receive channel is disabled and powered down. any disabled channel will indicate a constant /lfix output. when a disabled receive channel is re-enabled, the status of the associated lfix output and data on the parallel outputs for the associated channel may be indeterminate for up to 10 ms. after powering the chip, the transmitter may assume either a positive or negative value for its initial running disparity. upon transmission of any transmission character, the transmitter will select the proper version of the transmission character when oele is high and boe[x] is high, the associated serial driver is enabled. when oele is high and boe[x] is low, the associated driver is disabled and powered down. if both outputs for a channel are disabled, the internal logic for that channel is powered down. when oele returns low, the values present on the boe[7:0] inputs are latched in the output enable latch. output bus each receive channel presents a 12-signal output bus consisting of: a 10-bit data bus a comma detect indicator a parity bit. the receive decoder assigns the bit values per table 7 . the externally encoded data, the rxdx[0] corresponds to the msb of the 10 bit data. the signals present on this output bus are shown in table 8 . the framed 10-bit value is presented to the associated output register, along with a status output indicating if the character in the output register matches the selected framing characters. the comdetx status outputs operate the same regardless of the bit combination selected for character framing by the framchar input. characters in table 5 will cause comdet assertion, all others characters are mapped to invalid characters. comdetx is high when the character in the output register of the associated channel contains the selected framing character at the proper character boundary, and low for all other bit combinations. when the low-latency framer and half-rate receive port clocking are enabled, rfmode and rxrate are both low, the framer will stretch the recovered clock to the next 20-bit boundary such that the rising edge of rxclkx+ occurs when comdet is present on the associated output bus. when the standard framer is enabled and half-rate receive port clocking are enabled, rfmode is not low and rxrate is low, the output clock is not modified, but a single pipeline stage may be added or subtracted from the data stream by the framer logic such that the rising edge of rxclkx+ occurs when comdet is present on the associated output bus. this adjustment only occurs when the framer for that channel is enabled (rfenx is high). when the framer is disabled, the table 7. output register bit assignments [4] signal name rxstx[2] (lsb) comdetx rxstx[1] doutx[0] rxstx[0] doutx[1] rxdx[0] doutx[2] rxdx[1] doutx[3] rxdx[2] doutx[4] rxdx[3] doutx[5] rxdx[4] doutx[6] rxdx[5] doutx[7] rxdx[6] doutx[8] rxdx[7] (msb) doutx[9] note: 4. the rxopx outputs are also driven from the associated output reg- ister, but their interpretation is under the separate control of parctl. table 8. output register bit assignments signal name bus weight 10b name rxopx [5] comdet [5] rxdx[0] (lsb) 2 0 a [6] rxdx[1] 2 1 b rxdx[2] 2 2 c rxdx[3] 2 3 d rxdx[4] 2 4 e rxdx[5] 2 5 i rxdx[6] 2 6 f rxdx[7] 2 7 g rxdx[8] 2 8 h rxdx[9] (msb) 2 9 j 5. the rxopx and comdetx outputs are also driven from the associated output register, but their generation and interpretation are separate from the data bus. 6. lsb will be shifted in first.
cyp15g0402dx preliminary document #: 38-02023 rev. *b page 16 of 27 clock boundaries are not adjusted, and comdetx may be active during the rising edge of rxclkx ? . parity generation in addition to the ten data and comdetx status bits that are output on each channel, an rxopx output is also available on that channel. the cyp15g0402dx to supports odd parity generation for each channel. to handle a wide range of system environments, the cyp15g0402dx supports two forms of parity and no parity. parity on the rxdx[9:0] character parity on the rxdx[9:0] character and comdetx status. these modes differ in the number bits which are included in the parity calculation. only odd parity is provided which ensures that at least one bit of the data bus is always a logic-1. those bits covered by parity generation are listed in table 9 . parity generation is enabled through the 3-level select parctl input. when parctl is low, parity checking is disabled, and the rxopx outputs are all disabled (high-z). when parctl is mid, odd parity is generated for the rxdx[9:0] bits. when parctl is high, odd parity is generated for both the rxdx[9:0] bits and the associated comdetx signal. jtag support the cyp15g0402dx contains a jtag port to allow system level diagnosis of device interconnect. of the available jtag modes, only boundary scan is supported. this capability is present only on the lvttl inputs and outputs and refclk. the high-speed serial signals are not part of the jtag test chain. jtag id the jtag device id for the cyp15g0402dx is ? 0c801069 ? hex. 3-level select inputs each 3-level select input reports as two bits in the scan register. these bits report the low, mid, and high state of the associated input as 00, 10, and 11, respectively. table 9. output register parity generation signal name receive parity generate mode (parctl) low [7] mid high comdetx x [8] rxdx[0] x x rxdx[1] x x rxdx[2] x x rxdx[3] x x rxdx[4] x x rxdx[5] x x rxdx[6] x x rxdx[7] x x rxdx[8] x x rxdx[9] x x notes: 7. receive path parity output drivers are disabled when parctl is low. 8. when bist is not enabled,comdetx is usually driven to a logic 0, but will be driven high when the character in the output buffer is the selected framing character.
cyp15g0402dx preliminary document #: 38-02023 rev. *b page 17 of 27 maximum ratings above which the useful life may be impaired. for user guidelines, not tested. storage temperature ? 65 c to +150 c ambient temperature with power applied ? 55 c to +125 c supply voltage to ground potential ? 0.5v to +3.8v output current into lvttl outputs (low)30 ma dc input voltage- ? 0.5v to v cc +0.5v static discharge voltage > 2000 v (per mil-std-883, method 3015) latch-up current > 200 ma operating range range ambient temperature v cc commercial 0 c to +70 c 3.3v 5% industrial ? 40 c to +85 c 3.3v 5% cyp15g0402dx dc electrical characteristics over the operating range parameter description test conditions min. max. unit lvttl compatible outputs v oht output high voltage i oh = ? 4 ma, vcc = min. 2.4 vcc v v olt output low voltage i ol = 4 ma, vcc = min. 0 0.4 v i ost output short circuit current v out = 0v [9] ? 15 ? 35 ma i ozl high-z output leakage current ? 20 20 a lvttl compatible inputs v iht input high voltage 2.0 vcc+0.3 v v ilt input low voltage ? 0.5 0.8 v i iht input high current refclk input, v in = v cc +1.5 ma other inputs, v in = v cc +40 a i ilt input low current refclk input, v in = 0.0v ? 1.5 ma other inputs, v in = 0.0v ? 40 a i ihpdt input high current with internal pull-down v in = v cc +200 a i ilput input low current with internal pull-up v in = 0.0v ? 200 a lvdiff inputs: refclk v diff input differential voltage 400 v cc mv v ihhp highest input high voltage 1.0 v cc v v illp lowest input low voltage gnd v cc /2 v v com common mode range 0.8 v cc ?1 .2v v 3-level inputs v ihh three-level input high voltage min. v cc max. 0.87 * v cc v cc v v imm three-level input mid voltage min. v cc max. 0.47 * v cc 0.53 * v cc v v ill three-level input low voltage min. v cc max. 0.0 0.13 * v cc v v ihh input high current vin = vcc 200 a v imm input mid current vin = vcc/2 ? 50 50 a v ill input low current vin = gnd ? 200 a parameter description test conditions max. unit c inttl ttl input capacitance t a = 25 c, f 0 = 1 mhz, v cc = 3.3v 7 pf c inpecl pecl input capacitance t a = 25 c, f 0 = 1 mhz, v cc = 3.3v 4 pf note: 9. outputs tested one output at a time, output shorted for less than one second, much less than 10% duty cycle.
cyp15g0402dx preliminary document #: 38-02023 rev. *b page 18 of 27 differential cml serial outputs: outa , outb , outc , outd typical max unit v ohc output high voltage 100 ? differential load v cc ? 0.5 v cc ? 0.2 v 150 ? differential load v cc ? 0.5 v cc ? 0.2 v v olc output low voltage 100 ? differential load v cc ? 1.1 v cc ? 0.7 v 150 ? differential load v cc ? 1.1 v cc ? 0.7 v v odif output differential voltage |(out+) ? (out ? )| 100 ? differential load 450 800 mv 150 ? differential load 560 1000 mv differential serial line receiver inputs: ina , inb , inc , ind vi diff] input differential voltage |(in+) ? (in ? )| 100 1200 mv v ihe highest input high voltage v cc v v ile lowest input low voltage v cc ? 2.0 v i ihe input high current v in = v ihh max. 1000 a i ile input low current v in = v ill min. ? 700 a iv com [10] input common mode range ((vcc-2.0)+.05)min., ((vcc-.05)max. 1.25 3.25 v miscellaneous typical max. unit i cc [11] power supply current commercial 860 1100 ma industrial tbd tbd ma cyp15g0402dx transmitter lvttl switching characteristics over the operating range parameter description min. max. unit f ts txclkx clock cycle frequency 20 150 mhz t txclk txclkx period 6.66 50 ns t txclkh txclkx high time 2.2 ns t txclkl txclkx low time 2.2 ns t txclkr [12] txclkx rise time 0.3 1.7 ns t txclkf [12] txclkx fall time 0.3 1.7 ns t txds transmit data set-up time to txclkx (txcksel low) 2 ns t txdh transmit data hold time from txclkx (txcksel low) 1 ns f tos txclko clock cycle frequency equals 1x or 2x refclk frequency 20 150 mhz t txclko txclko period 6.66 50 ns t txclkod txclkop duty cycle centered with 60 per cent high time -0.7 +0.7 ns t txclkod txclkon duty cycle centered with 40 per cent high time -0.0 1.5 ns t txods transmit data set-up time to txclko (txcksel = low) 1.5 ns t txodh transmit data hold time from txclko (txcksel = low) 1.5 ns t txrss txrst set-up time to txclko 3 ns t txrsh txrst hold time from txclko 1 ns notes: 10. this is the minimum difference in voltage between the true and the complement input required to ensure detection of a logic 1 or logic 0. a logic true occurs when the input + is above the -input. a logic zero is true when the +input is below the voltage of - input. 11. maximum current is measured with v cc = max, rfen = low, with all serial channels sending a constant alternations 01 pattern, and the output unloaded. typical is measured under same conditions, except that power is 3.3v. 12. paralleled data output specifications are only valid if all outputs are loaded with similar dc and ac loads.
cyp15g0402dx preliminary document #: 38-02023 rev. *b page 19 of 27 cyp15g0402dx transmit serial outputs and tx pll characteristics over the operating range parameter description condition min. max. unit t b bit time 5000 660 ps t rise cml output rise time 20 ? 80% (cml test load) [13] spdsel = high 50 270 ps spdsel = mid 100 500 ps spdsel = low 200 1000 ps t fall cml output fall time 80 ? 20% (cml test load) [13] spdsel = high 50 270 ps spdsel = mid 100 500 ps spdsel = low 200 1000 ps t dj deterministic jitter (peak-peak) [14, 17 0.1 ui t tj total jitter ( ) [15, 17] 0.2-1.0gbps 0.2 ui 1.0-1.5gbps 192 ps t txlock transmit pll lock to refclk tbd tbd ns receive serial inputs and cdr pll characteristics over the operating range parameter description min. max. unit t rxlock receive pll lock to input data stream 10 ms receive pll lock to input data stream 2500 ui t rxunlock receive pll unlock rate tbd tbd ns t sa static alignment [16] ps t efw error-free window [14, 17, 18] 0.75 ui notes: 13. refclk has no phase or frequency relationship with rxclk and only acts as a centering reference to reduce clock synchronizat ion time. refclk must be within 200- ppm ( 0.02%) of the transmitter pll reference (refclk) frequency, necessitating a 100-ppm crystal. 14. while sending continuous k28.5s, outputs loaded to a balanced 100 ? load, over the operating range. 15. while sending continuous k28.7s, after 100,000 samples measured at the cross point of differential outputs, time referenced to refclk input, over the operating range. 16. static alignments is a measure of the alignment of the receiver sampling point to the center of a bit. static alignment is m easured by sliding one bit edge in 3,000 nominal transitions until a character error occurs. 17. receiver ui is calculated as 1/fref*10 when rxrate = low if no data is being received of the remote transmitter. if data is being received it is equal to 1/transmit serial bit rate. 18. error free window is a measure of the time window between the bit centers where a transition may occur without causing a sam pling error. it is measured over the operational range.
cyp15g0402dx preliminary document #: 38-02023 rev. *b page 20 of 27 hotlink ii transmitter switching waveforms note: 19. when refclk is configured for half-rate operation (txrate = low) and data is captured using refclk instead of a txclkx clock (txcksel = low), data is captured using the rising edges of the internally synthesized character rate clock. while the rising edge of this clock (txclko) is aligned to the rising edge of reflck, it is not aligned to the falling edge of refclk. txclkx txdx[9:0] t txdh t txds t txclk t txclkh t txclkl transmit interface write timing txopx txcksel low refclk transmit interface t refclk t refh t refl t trefds t trefdh write timing txcksel = low txrate = low txdx[9:0], txopx txclko t txodh t txods t txclko t txoh t txol transmit interface write timing txcksel = low txrate = high (internal) refclk t txodh t txods t refclk t refl t refh note txopx txdx[9:0],
cyp15g0402dx preliminary document #: 38-02023 rev. *b page 21 of 27 hotlink ii receiver switching waveforms rxclkx+ rxdx[9:0], comdetx, t rxdh t rxds t rxclkp t rxclkh t rxclkl receive interface read timing rxopx rxrate = low rxclkx ? rxclkx+ rxdx[9:0], comdetx, t rxdh t rxds t rxclkp t rxclkh t rxclkl receive interface read timing rxopx rxcksel = high rxrate = low rxclkx ? ina , inb t b /2 ? t sa t b /2 ? t sa static alignment sample window ina inb t b t efw bit center bit center error-free window
cyp15g0402dx preliminary document #: 38-02023 rev. *b page 22 of 27 cyp15g0402dx receiver lvttl switching characteristics over the operation range parameter description min. max. unit f rs rxclkx clock output frequency 20 150 mhz t rxclkp rxclkx period 6.66 50 ns t rxclkh rxclkx high time (rxrate = high) 1.5 24 ns rxclkx high time (rxrate = low) 5 25 ns t rxclkl rxclkx low time (rxrate = high) 1.5 24 ns rxclkx low time (rxrate = low) 5 25 ns t rxclkd rxclkx duty cycle centered with a 50% high time ? 1.0 +1.0 ns t rxclkr [20] rxclkx rise time 0.3 1.2 ns t rxclkf [20] rxclkx fall time 0.3 1.2 ns t rxdv- [21] status and data valid time from rxclkx (rxcksel high or mid) 5ui ? 1.5 ns t rxdv+ [21] status and data valid time from rxclkx (rxcksel high or mid) 5ui ? 1.8 ns t rxdv- [21] status and data invalid time from rxclkx (half-rate clock) 5ui ? 1.0 ns t rxdv+ [21] status and data invalid time from rxclkx (half-rate clock) 5ui ? 2.3 ns cyp15g0402dxa refclk switching characteristics over the operating range parameter description min. max. unit f ref refclk clock output frequency 20 150 mhz t refclk refclk period 6.6 100 ns t refh refclk high time (txrate = high) 5.9 24 ns refclk high time (txrate = low) 2.9 35 ns t refl refclk low time (txrate = high) 5.9 24 ns refclk low time (txrate = low) 2.9 35 ns t refd refclk duty cycle 30 7 0 % t ref rxclkx rise time 2 ns t reff rxclkx fall time 2 ns t refds [21] transmit data hold time to refclk (txcksel = low) 2 ns t refdh [21] transmit data hold time to refclk (txcksel = low 1 ns t rrefda [21] receive data access time from refclk (rxcksel = low) 9.5 ns t rrefdv receive data valid time from refclk (rxcksel = low) 4.0 ns t rrefdv- receive data valid time from rxclka (rxcksel = low) 1.5 ns t rrefdv+ receive data valid time from rxclka (rxcksel = low) 1.5 ns t rrefcdv- receive data valid time from rxclkc (rxcksel = low) 3.0 ns t rrefcdv+ receive data valid time from rxclkc (rxcksel = low) 0.5 ns t refrx refclk frequency referenced to received clock period -0.02 +0.02 % notes: 20. tested initially and after any design or process changes that may affect these parameters, but not 100% tested. 21. parallel data output or input specifications are only valid if all signals are loaded with similar dc and ac loads.
cyp15g0402dx preliminary document #: 38-02023 rev. *b page 23 of 27 chip pin numbers pin name type a01 inc- cmlin a02 outc- cmlout a03 nc a04 nc a05 vcc power a06 ind- cmlin a07 outd- cmlout a08 gnd gnd a09 nc a10 nc a11 ina- cmlin a12 outa- cmlout a13 gnd gnd a14 nc a15 nc a16 vcc power a17 inb- cmlin a18 outb- cmlout a19 nc a20 nc b01 inc+ cmlin b02 outc+ cmlout b03 nc b04 nc b05 vcc power b06 ind+ cmlin b07 outd+ cmlout b08 gnd gnd b09 nc b10 nc b11 ina+ cmlin b12 outa+ cmlout b13 gnd b14 nc b15 nc b16 vcc power b17 inb+ cmlin b18 outb+ cmlout b19 nc b20 nc c01 tdi lvttlinu c02 tms lvttlinu c03 lpenc lvttlin c04 lpenb lvttlin c05 vcc power c06 parctl lvlsel c07 sdasel lvlsel c08 gnd gnd c09 boe<7> lvttlinu c10 boe<5> lvttlinu c11 boe<3> lvttlinu c12 boe<1> lvttlinu c13 gnd gnd c14 gnd gnd c15 gnd gnd c16 vcc power c17 txrate lvttlind c18 rxrate lvttlind c19 nc c20 tdo ltout3st pin name type d01 tclk lvttlind d02 /trstz lvttlinu d03 lpend lvttlin d04 lpena lvttlin d05 vcc power d06 rfmode lvlsel d07 spdsel lvlsel d08 gnd gnd d09 boe<6> lvttlinu d10 boe<4> lvttlinu d11 boe<2> lvttlinu d12 boe<0> lvttlinu d13 gnd gnd d14 gnd gnd d15 gnd gnd d16 vcc power d17 nc d18 rxle lvttlinu d19 nc d20 nc e01 vcc power e02 vcc power e03 vcc power e04 vcc power e17 vcc power e18 vcc power e19 vcc power e20 vcc power f01 txperc lvttlout f02 txopc lvttlinu f03 txdc[0] lvttlin f04 rxcksel lvlsel f17 bistle lvttlinu f18 rxdb[0] lvttlout f19 rxopb ltout3st f20 rxdb[1] lvttlout g01 txdc[7] lvttlin g02 xcksel lvlsel g03 txdc[4] lvttlin g04 txdc[1] lvttlin g17 gnd gnd g18 oele lvttlinu g19 framchar lvlsel g20 rxdb[3] lvttlout h01 gnd gnd h02 gnd gnd h03 gnd gnd h04 gnd gnd pin name type h17 gnd gnd h18 gnd gnd h19 gnd gnd h20 gnd gnd j01 txdc[9] lvttlin j02 txdc[5] lvttlin j03 txdc[2] lvttlin j04 txdc[3] lvttlin j17 comdetb lvttlout j18 rxdb[2] lvttlout j19 rxdb[7] lvttlout
cyp15g0402dx preliminary document #: 38-02023 rev. *b page 24 of 27 pin name type j20 rxdb[4] lvttlout k01 rxdc[4] lvttlout k02 rxclkc- lvttlout k03 txdc[8] lvttlin k04 /lfic lvttlout k17 rxdb[5] lvttlout k18 rxdb[6] lvttlout k19 rxdb[9] lvttlout k20 rxclkb+ lvttliod l01 rxdc[5] lvttlout l02 rxclkc+ lvttliod l03 txclkc lvttlind l04 txdc[6] lvttlin l17 rxdb[8] lvttlout l18 /lfib lvttlout l19 rxclkb- lvttlout l20 txdb[6] lvttlin m01 rxdc[6] lvttlout m02 rxdc[7] lvttlout m03 rxdc[9] lvttlout m04 rxdc[8] lvttlout m17 txdb[9] lvttlin m18 tddb[8] lvttlin m19 txdb[7] lvttlin m20 txclkb lvttlin n01 gnd gnd n02 gnd gnd n03 gnd gnd n04 gnd gnd n17 gnd gnd n18 gnd gnd n19 gnd gnd n20 gnd gnd p01 rxdc[3] lvttlout p02 rxdc[2] lvttlout p03 rxdc[1] lvttlout p04 rxdc[0] lvttlout p17 txdb[5] lvttlin p18 txdb[4] lvttlin p19 txdb[3] lvttlin p20 txdb[2] lvttlin r01 comdetc lvttlout r02 rxopc ltttlout r03 txperd lvttlout pin name type r04 txopd lvttlinu r17 txdb[1] lvttlin r18 txdb[0] lvttlin r19 txopb lvttlinu r20 txperb lvttlout t01 vcc power t02 vcc power t03 vcc power t04 vcc power t17 vcc power t18 vcc power t19 vcc power t20 vcc power u01 txdd[0] lvttlin u02 txdd[1] lvttlin pin name type u03 txdd[2] lvttlin u04 txdd[9] lvttlin u05 vcc power u06 rxdd[4] lvttlout u07 rxdd[3] lvttlout u08 gnd gnd u09 rxopd ltout3st u10 rfenc lvttlind u11 refclk- peclin u12 txda[1] lvttlin u13 gnd gnd u14 txda[4] lvttlin u15 txda[8] lvttlin u16 vcc power u17 rxda[4] lvttlout u18 rxopa lvttlout u19 comdeta lvttlout u20 rxda[0] lvttlout v01 txdd[3] lvttlin v02 txdd[4] lvttlin v03 tddd[8] lvttlin v04 rxdd[8] lvttlout v05 vcc power v06 rxdd[5] lvttlout v07 rxdd[1] lvttlout v08 gnd gnd v09 comdetd lvttlout v10 rfend lvttlod3 v11 refclk+ peclin v12 rfenb lvttlod3 v13 gnd gnd v14 txda[3] lvttlin v15 txda[7] lvttlin v16 vcc power v17 rxda[9] lvttlout v18 rxda[5] lvttlout v19 rxda[2] lvttlout v20 rxda[1] lvttlout w01 txdd[5] lvttlin w02 txdd[7] lvttlin pin name type w03 /lfid lvttlout w04 rxclkd- lvttlout w05 vcc power w06 rxdd[6] lvttlout w07 rxdd[0] lvttlout w08 gnd gnd w09 txclko- lvttlout w10 /txrst lvttlinu w11 txopa lvttlinu w12 rfena lvttlin w13 gnd gnd w14 txda[2] lvttlin w15 txda[6] lvttlin w16 vcc power w17 /lfia lvttlout w18 rxclka- lvttlout w19 rxda[6] lvttlout w20 rxda[3] lvttlout y01 txdd[6] lvttlin
cyp15g0402dx preliminary document #: 38-02023 rev. *b page 25 of 27 pin name type y02 txclkd lvttlind y03 rxdd[9] lvttlout y04 rxclkd+ lvttliod y05 vcc power y06 rxdd[7] lvttlout y07 rxdd[2] lvttlout y08 gnd gnd y09 txclko+ lvttlout y10 nc gnd y11 txclka lvttlind pin name type y12 txpera lvttlout y13 gnd gnd y14 txda[0] lvttlin y15 txda[5] lvttlin y16 vcc power y17 txda[9] lvttlin y18 rxclka+ lvttliod y19 rxda[8] lvttlout y20 rxda[7] lvttlout ordering information speed ordering code package name package type operating range standard cyp15g0402dx-bgc bl256 256-ball thermally enhanced ball grid array commercial standard CYP15G0402DX-BGI bl256 256-ball thermally enhanced ball grid array industrial
cyp15g0402dx preliminary document #: 38-02023 rev. *b page 26 of 27 ? cypress semiconductor corporation, 2002. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do i ng so indemnifies cypress semiconductor against all charges. package diagram hotlink ii, and multiframe are trademarks of cypress semiconductor corporation. ibm is a registered trademark of international business machines. escon is a registered trademark of international business machines. ficon is a trademark of international business machines. 256-lead thermally enhanced l2bga (27 x 27 x 1.52 mm) bl256 51-85123-*c
cyp15g0402dx preliminary document #: 38-02023 rev. *b page 27 of 27 document title: cyp15g0402dx quad hotlinkii ? serdes document number: 38-02023 rev. ecn no. issue date orig. of change description of change ** 108363 07/11/01 tme new data sheet *a 108915 07/31/01 amv changed name of part from phy to serdes *b 112986 03/01/02 tps changed common mode input specs to match 401d part pp. 17, 18 added engineering changes to half-rate timing. p. 22 updated the spec as per meeting with engineering pp. 20 ? 23 changed the refclock input to vlttl both inputs p. 9 addition of txclko n and the txclko p specs p. 22 changed the txclko clock output to reflect the new timing p. 22 changed the half clock drawing so that the valid time was at clock edges changed the input power input p. 21, p. 22 max. power changed the spec for serial output levels at the different terminations. changed the common mode input range of serial input increased the serial input current under the conditions of v cc and min. added to the duty cycle of transmit and receiver clock signals changed rise time of the serial inputs and receiver changed half-rate timing drawing from not valid at clock edges to valid at clock edges max. voltage reduced from 4.2 to 3.8 matched the common specs with the family of parts pp. 21 ? 24 changed max output current to 35 ma p. 20 corrected period timing of min. clock from 100 ns to 50 ns p. 19 added ? preliminary ? added pin rxcksel to the pin layout p. 6, 7 to pin layout and pin descriptions change min. clock frequency change the front pages remove decoder command from p. 16, as it is no longer used.

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